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EnDat Interface Encoder Data Acquisition Design

The absolute encoder utilizes natural binary, cyclic binary (Gray code), or PRC code to optically convert the physical markings on a code disc. It transforms the rotational angle of the connected shaft into a corresponding sequence of electrical pulses, outputting it as a digital signal. This technology offers advantages such as compact size, high precision, digital interface, and absolute positioning. It is widely used in radar systems, turntables, robotics, CNC machines, and high-precision servo systems. The data output from an absolute encoder typically follows a synchronous serial format. The EnDat interface, developed by HEIDENHAIN, is a digital, full-duplex synchronous serial interface specifically designed for encoders. It not only transmits position values for both incremental and absolute encoders but also allows for the transfer or updating of information stored within the encoder or the storage of new data. Due to its serial transmission method, only four signal lines are required. Under the excitation of a clock signal from the downstream electronic device, the data is transmitted synchronously. The type of data (position value, parameter, diagnostic information, etc.) is determined by the mode command sent by the downstream device to the encoder. **Introduction to the EnDat Interface** 1. **Key Features of the EnDat Interface** - **High performance at low cost**: The universal interface supports all incremental and absolute encoders, offering economical power consumption, compact design, fast system setup, and floating zero points based on offset values. - **Enhanced signal quality**: Internal optimization improves system accuracy, providing better contour accuracy for CNC machines. - **Improved practicality**: Automatic system configuration, digital signals enhancing reliability, monitoring and diagnostic features for safety, and redundancy code verification for reliable signal transmission. - **Enhanced system security**: Two separate location and error bits, data checksums, and responses ensure secure communication. - **Support for advanced technologies**: High resolution, short control cycles, 16 MHz clock speed, and safety-oriented design make it suitable for direct drive applications. ![EnDat Interface Encoder Data Acquisition Schematic](http://i.bosscdn.com/blog/20/08/12/02082734238.jpg) **2. Performance Enhancements in EnDat 2.2 Encoders** - Simultaneous transmission of position values and additional information, with the type of additional data determined by address selection codes. - Integrated memory areas include manufacturer parameters, OEM parameters, operating parameters, and status information, facilitating system configuration. - Full digital transmission with internal 14-bit subdivision for improved signal quality and higher resolution. - Advanced monitoring and diagnostics: alerts for light source failure, insufficient signal amplitude, incorrect position calculation, voltage issues, and excessive current draw. - Wide voltage range (3.6–14V) and high-speed transmission (16 MHz). **3. Timing and OEM Data Storage** During each frame of synchronous data transmission, a data packet is sent. The cycle starts with the first falling edge of the clock, and the position value is calculated. After two clock pulses (2T), the downstream device sends the "encoder transmit position value" command. Once the absolute position is calculated, the encoder begins transmitting data from the start bit. Error bits F1 and F2 (exclusive to EnDat 2.2) are used for fault monitoring and indicate potential encoder failures. The exact cause of the failure is stored in the "operational" memory area and can be queried by the downstream device. Position values are transmitted starting from the lowest bit, with the data length depending on the encoder type. The number of clock pulses needed to transmit the position value is stored in the manufacturer’s parameters. The transmission ends with a cyclic redundancy check (CRC). If additional information is included, it is sent immediately after the position value, also ending with a CRC. The content of the additional information depends on the selected memory area and is transmitted during the next sampling period until a new area is selected. At the end of the data word, the clock signal must be set high. After a recovery time (10–30 μs or 1.25–3.75 μs for EnDat 2.2), the data line returns to low, allowing new data to begin. ![Position Value Transmission Without Additional Information](http://i.bosscdn.com/blog/20/08/12/02082734377.jpg) ![Position Value Transmission With Additional Information](http://i.bosscdn.com/blog/20/08/12/02082734969.jpg) Encoders provide various memory areas for parameters that can be read by downstream devices. These areas can be written by the manufacturer, OEM, or even the end user, with some areas being write-protected. Different encoder series support different OEM memory areas and address ranges, so each encoder must read the OEM memory allocation. Therefore, subsequent circuits should be programmed using relative addresses rather than absolute ones. **4. Circuit Design for Follow-up Electronic Devices** Users can design their own interface circuits according to the EnDat protocol and electrical characteristics. HEIDENHAIN also offers specific data processing chips for users to choose from. Using these chips simplifies the design process, as users only need to configure the FPGA registers and send instructions in the chip's acceptable format to obtain the desired data. By following the RS-485 standard for differential signaling, bidirectional data transmission between the encoder and downstream devices is possible under the excitation of a synchronous clock issued by the downstream device. **5. FPGA + Software Macros** MAZet, a partner of HEZEHAN, provides EnDat software macros for Xilinx Virtex and Spartan series, as well as Altera Acex and Cyclone series. Custom soft cores can be provided upon customer request. These soft cores implement all functions of the EnDat interface. Users can perform 8-bit or 16-bit data transmission with a microcontroller via a 6-bit address line and a 16-bit data line. Below is the module diagram and circuit design for the FPGA. ![FPGA Module Diagram](http://i.bosscdn.com/blog/20/08/12/02082734300.jpg) ![Encoder and Subsequent Circuit Connection Module Diagram](http://i.bosscdn.com/blog/20/08/12/02082734529.jpg) **6. Conclusion** HEIDENHAIN’s EnDat interface has been widely adopted across industries and has now reached a new level of performance. The bidirectional EnDat 2.2 interface now operates at a clock frequency of 16 MHz, meeting the demands of high dynamic applications, especially in the electronics industry. Increasing the clock frequency from 8 MHz to 16 MHz significantly reduces the time required to read position information and shortens the control loop cycle. Simple and cost-effective system designs offer convenience, powerful functionality, versatility, and forward-looking security concepts that guide the continuous advancement of coding control technology.

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